1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory-device and a writing method thereof. In particular, the present invention is concerned with a non-volatile semiconductor memory device to be mounted on the same substrate as that of a semiconductor device having a logical operation function which is typified by a microcomputer.
2. Description of the Related Art
By mounting a non-volatile semiconductor memory cell on the same silicon substrate as that of a semiconductor device for logical operation it becomes possible to implement a semiconductor device of a high-level function. Such high-level function semiconductor devices are used as built-in type microcomputers widely in industrial machines, home electric appliances and devices mounted on automobiles. Generally, in the non-volatile memory are stored programs which the microcomputer requires, and the programs are read out and used as necessary. As an example of a cell structure of the non-volatile memory suitable for the mixed mounting together with the semiconductor device for logical operation there is mentioned a split gate type memory cell comprising a MOS transistor for selection and a MOS transistor for storage. This structure is mainly adopted in the mixed mounting because a small area of a memory controlling peripheral circuit suffices. As examples of related technical literatures are mentioned Japanese Patent Laid Open Nos. Hei 5(1993)-48113 and Hei 5(1993)-121700, IEEE, VLSI Technology Symposium, 1994 Proceedings, pp. 71 to 72, and IEEE, VLSI Technology Symposium, 1997 Proceedings, pp. 63 to 64, (Patent Document 1, Patent Document 2, Non-Patent Document 1, Non-Patent Document 2, respectively).
As charge storing methods in MOS type transistors for storage there are known a floating gate method (disclosed in Patent Literature 2 and Non-Patent Literature 1) wherein an electric charge is stored in an electrically isolated and electrically conductive polycrystalline silicon and a MONOS method (disclosed in Patent Literature 1 and Non-Patent Literature 2) wherein an electric charge is stored in an insulating film having a charge storing property such as silicon nitride film.
The floating gate method is in wide use, for example, portable telephone-oriented flash memories for the storage of programs and large-capacity flash memories for the storage of data and is superior in charge retention characteristic. However, according to scaling, it becomes difficult to ensure a capacitive coupling ratio necessary for controlling the potential of a floating gate and the structure is becoming more and more complicated. To suppress the leakage of held charge it is considered necessary that the thickness of oxide film which surrounds the floating gate be about 8 nm or more. Thus, a limit of the scaling aiming at high speed and high integration is around the corner. Because of storage of an electric charge in a conductor, an oxide film defect acting as leak path easily exerts a bad influence, and in a memory cell involving an oxide film defect, its charge retention time is extremely deteriorated. On the other hand, the MONOS method is generally inferior in charge retention characteristic to the floating gate method and a threshold voltage tends to drop in terms of a logarithm of time. For this reason, although the MONOS method is an old-established method, it has so far been practically applied to only limited products. In the MONOS method, however, since an electric charge is stored in an insulator, a inherently strong resistance to an oxide film defect is attained; besides, a thin oxide film of 8 nm or less is also employable and is thus suitable for scaling, it is easy to predict reliability because an extreme deterioration of the charge holding life does not occur, and the memory cell structure is simple and easy to be mixed with a logical circuit section. Consequently, the MONOS method is again being noted with the recent progress of device scaling.
Particularly, as a split gate structure suitable for device scaling there is known a self-align structure wherein the MOS transistor is formed as a side wall (Patent Document 1 and Non-Patent Document 1). In this case, an alignment margin for photolithography is not necessary and the gate length of the transistor formed by self-alignment can be made below the minimum resolution size in lithography. Therefore, a finer memory cell can be implemented in comparison with the conventional structure wherein two types of transistors are each formed using another mask.
Among split gate type memory cells using self-alignment, for example the cell wherein a self-aligned gate side is formed by MONOS structure, which is disclosed in Non-Patent Document 2, is suitable for mixed mounting together with a high-speed logical circuit section. A section of this memory cell is shown in FIG. 1. On a side wall of a select gate 12 is formed a memory gate 11 by an ONO film comprising SiO2 film 13, SiN film 14 and SiO2 film 15 and by a polysilicon electrode of a side wall structure. A silicide layer 16-1 is formed over diffusion area 1, 5, select gate 12 and memory gate 11. An example of this structure is shown in Japanese Patent Application No. 2002-352040 filed by the same applicant as the applicant of the present case and which is pending.
According to the structure of this memory cell, the select gate side is formed first, so that a gate oxide of the select gate and a gate oxide film in the logical circuit section which is formed at the same time, can be formed in a high quality condition of a silicon substrate interface. Since a thin gate dielectric transistor for high-speed operation, which is sensitive to the interface quality, can be formed first, the performance of the logical circuit section and that of the select gate transistor to be mounted together are improved. Stored information can be read by only the operation of the select gate transistor of high performance, and since all of transistors connected thereto can also be formed as a low voltage type of thin gate dielectric, it is possible to attain both high speed read operation and reduction of the circuit area.
FIG. 2 shows an array using the split gate type MONOS memory cells in question. Each cell shares a diffusion area (hereinafter referred to as “source”) adjacent to the memory gate 11 with an opposed memory cell and source lines 1 run in parallel with word lines. In the word line direction are arranged two types of word lines which as memory gate 2 type and select gate 3 type. Bit lines 4 perpendicular thereto are connected to diffusion areas (“drain” hereinafter) adjacent to the select gates 12 in the cells.
FIG. 3 shows typical voltage conditions in operation. Write is performed using a source side injection method (SSI method). That is, with about 12V and 5V applied to the memory gate and the source respectively, the select gate is inverted weakly and electrons are injected by a strong electric field developed between the select gate and the memory gate. Erase is performed by a hot hole injection method using a band-to-band tunneling (BTBT method). Reverse bias voltages of about −5V and 7V are applied to the memory gate and the source, respectively, and hot holes based on a band-to-band tunneling are created with a strong electric field developed at an end of the diffusion area and are injected into the memory gate. For reading stored information, 1.5V is applied to the memory gate and the select gate and 1V is applied to the drain and is made on the basis of the magnitude of an electric current flowing through the drain.
[Patent Document 1]
Japanese Patent Laid Open No. Hei 5(1993)-48113 (FIG. 1)
[Patent Document 2]
Japanese Patent Laid Open No. Hei 5(1993)-121700 (representative drawing and description of the prior art)
[Non-Patent Document 1]
IEEE, VLSI Technology Symposium, 1994 Proceedings, pp. 71 to 72 (FIG. 1)
[Non-Patent Document 2]
IEEE, VLSI Technology Symposium, 1997 Proceedings, pp. 63 to 64 (FIG. 1)
In this connection, there is a problem that when an arbitrary memory cell is to be written, another memory cell on the same word line is erroneously written or erased depending on a bias condition in the course of transition from a stand-by state to a bias condition in a write state. Conversely, also at the time of transition from a write state to a stand-by state, an erroneous write or erase can occur for the same reason. Such an unintended erroneous write or erase is generally called disturb. The disturb includes a disturb caused by a non-selection bias which a memory cell lying in an unselected position within an array receives and a sequence disturb caused by a time-oriented bias condition during rise or fall of bias to a write state.
The sequence disturb will here be explained in more detail. FIG. 3 illustrates typical operation conditions. In the same figure, Read, Write, and Erase, show conditions during read, write, and erase, respectively. Vmg stands for an applied voltage to a first gate (i.e., memory gate), Vs stands for an applied voltage to a first impurity-diffused region (i.e., generally source region), Vcg stands for an applied voltage to a second gate (i.e., selection gate), Vd stands for an applied voltage to a second impurity-diffused region (i.e., drain region), and Vsub stands for an applied voltage to the substrate.
When a change is made from a stand-by state to the write state bias shown in FIG. 3, write is performed word line by word line and therefore first the memory gate line, selection gate line and source line in the word line direction are allowed to rise to the write state bias. Since the lines are different in load capacity and driver circuits connected thereto are different in ability and since there is a circuit used in common, generally the lines are not allowed to rise simultaneously, but are allowed to rise and fall in accordance with a preset sequence. At this time, when the memory gate line is first allowed to rise at the potential on the memory transistor side, electrons are injected with an electric field developed by a potential difference between the memory gate and the substrate and there occurs an erroneous write in a time zone until rise of the source line. Conversely, when the source line is first allowed to rise, a strong electric field is developed in the source-side diffusion layer in a time zone until rise of the source line and there occurs a weak BTBT hot hole injection (i.e., hot hole injection caused by a band-to-band tunneling) with consequent occurrence of an erroneous erase.
FIG. 4 shows schematically a relation between bias conditions and the resulting disturb, in which a memory gate voltage Vmg is plotted along the axis of ordinate and a source voltage Vs is plotted along the axis of abscissa. The units are all V. In a region 21 appearing in the same figure, there occurs Fowler-Nordheim (FN) tunneling electron injection with a high electric field on the memory gate side and the threshold voltage rises, that is, an erroneous write occurs. A region 22 is used for write under the condition that source-side injection (SSI) occurs depending on the electric current in the selection transistor. In a region 23, there occurs a lowering of the threshold voltage, that is, an erroneous erase occurs, because there occurs BTBT hot hole injection with the electric field of the source diffusion area or region. In transition from a stand-by state 24 to a write state 25, a path 26 in which Vmg is first allowed to rise passes the region 21 and therefore an erroneous write occurs, while a path 27 in which Vs is first allowed to rise passes the region 23 and therefore an erroneous erase occurs. Also at the time of voltage fall there occurs a sequence-based disturb for the same reason.
More particularly, a memory cell in which the threshold voltage drops due to the sequence disturb is an already-written memory cell on a selected word line, and the threshold voltage drops when the word line rising or falling bias passes the region 23 in FIG. 4. Conversely, a memory cell in which the threshold voltage rises is a memory cell which is in an erased state on a selected word line, and the threshold voltage rises when the word line rising or falling bias passes the region 21 in FIG. 4.
FIGS. 5 and 6 show measurement results of disturb quantities in the regions 21 and 23, respectively, in FIG. 4. In FIG. 5, the bias condition corresponds to the region 21 of Vmg=14V, Vs=1.5V and the axis of abscissa represents a data disturb time, while the axis of ordinate represents a threshold voltage in a state of erase. The threshold voltage in a state of erase rises at a disturb time of 10 μsec or more. Likewise, in FIG. 6, the bias condition corresponds to the region 23 in FIG. 4 with Vmg 1.5V, Vs=5V, and the threshold voltage in a state of write drops at a disturb time of 100 μsec or more. Since a series of operations for setting each terminal to a write state and resetting to the stand-by state requires a time of about 10 to 100 μsec, the above sequence disturbs can be a problem.
Further, the disturb of the sequence increases in proportion as the number of times of rise and fall of the word line increases. In verifying, write and read are repeated until the threshold voltage reaches a predetermined value, so that the rise and fall of the word line voltage are performed frequently and the disturb becomes more influential. The conventional circuit configuration requires that write be performed for alternate bit lines. Also in such a case, for write of one word line, rise and fall of the word line voltage are performed at least twice at both even- and odd-numbered bits and therefore the disturb of the sequence is more strongly influential.
Generally, the threshold voltage changes toward a thermal equilibrium state with the lapse of time, but if the threshold voltage is lower or higher than a value which has been set taking the charge holding life into account, information which has been stored within the life time is lost, that is, the reliability is deteriorated.